The present invention relates generally to memory devices, and more particularly, to a system for programming verification of memory devices.
The NAND type flash memory utilizes a storage architecture that is suitable for mass storage applications. Therefore, the device needs to have good reliability. However, the current NAND architecture cannot avoid generating wide voltage threshold (Vt) distributions because programming strength and time for each bit cannot be precisely controlled.
FIG. 1 shows a portion of a typical NAND memory device. As can be seen, every bit may have a different IR voltage drop with respect to an ARVSS line. Thus, when the chip goes to programming verify mode, some bits cannot pass the verify function even though every bit has received the same programming voltage. When bits fail to be programmed, the chip will return to the programming mode in an attempt to re-program and pass all the bits using a higher programming voltage. However, some bits may be overstressed by this process, and as a result, the device may be seriously damaged. Furthermore, such a programming technique results in a wide distribution of voltage thresholds.
Therefore, it would be desirable to have a way to program and verify a memory device without overstressing any bit logic and for achieving a narrow Vt distribution.
The present invention includes a system for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. For example, in one embodiment, the system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.
In one embodiment of the invention, a method is provided for performing program verification of memory cells in a NAND memory device to achieve selected Vt levels. The NAND memory device includes page buffers having disable gates that operate to enable or disable programming of selected memory cells. The method includes the steps of: (a) performing a programming cycle to program the memory cells to have the selected Vt levels; (b) setting a first verification level; (c) verifying that the memory cells have the selected Vt levels using the first verification level, wherein passed and failed memory cells are determined; (d) inhibiting, using the disable gates, the passed memory cells from further programming; (e) setting a second verification level; (f) verifying that the failed memory cells have a second selected Vt level using the second verification level, wherein second passed and second failed memory cells are determined; (g) adjusting a programming pulse to have a first strength level when the second passed memory cells are determined; (h) adjusting the programming pulse to have a second strength level when the second failed memory cells are determined; (i) re-programming the failed memory cells with the programming pulse; and (j) repeating steps (b) through (i) until the memory cells have the selected Vt levels.
In another embodiment of the invention, apparatus is provided for performing program verification in a NAND memory device. The apparatus includes a page buffer coupled to a bit line, the page buffer including a latch coupled to a data input and the latch produces an inhibit signal. The apparatus also includes a programming disable gate coupled between the bit line and a grounding gate, the programming disable gate is further coupled to receive the inhibit signal, wherein when the inhibit signal is in a first state the programming gate couples the bit line to the grounding gate, and wherein when the inhibit signal is in a second state the programming gate decouples the bit line and the grounding gate.